The present invention generally relates to complimentary metal-oxide semiconductors (CMOS) and metal-oxide-semiconductor field-effect transistors (MOSFET), and more specifically, to strain in semiconductor devices.
N-type field effect transistors (nFET) and p-type field effect transistors (pFET) are two types of complementary MOSFETs. The nFET, with n-doped source and drain junctions, uses electrons as the current carriers. The pFET, with p-doped source and drain junctions, uses holes as the current carriers.
Strain engineering is used to induce strain on the channel region of nFET and pFET devices. The strain can include a tensile strain or a compressive strain on the channel regions depending on the characteristics of the device. Crystalline materials such as crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) are orientated in a lattice structure each with a different lattice constant (lattice parameter). Typically, during an epitaxial growth process where a seed layer has a lattice constant that is different from the grown material layer, a strain is induced in the grown material layer. For example, when silicon is grown on a relaxed silicon germanium layer a tensile strain is induced in the grown silicon layer.